cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 1/7 MTF50P02J3 cystek product specification p-channel logic level enha ncement mode power mosfet MTF50P02J3 bv dss -20v i d -10a 58m r dson(max) features ? low gate charge ? simple drive requirement ? rohs compliant & halogen-free package equivalent circuit outline MTF50P02J3 to-252 absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds -20 gate-source voltage v gs 12 v continuous drain current @ t c =25 c -10 continuous drain current @ t c =100c i d -6.5 pulsed drain current *1 i dm -40 a total power dissipation @t c =25 30 total power dissipation @t c =100 pd 10 w operating junction and storage te mperature range tj, tstg -55~+175 c note : *1 . pulse width limited by maximum junction temperature g gate d drain g d s s source
cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 2/7 MTF50P02J3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 5 thermal resistance, junction-to-ambient, max r th,j-a 110 c/w characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -20 - - v v gs =0, i d =-250 a v gs(th) -0.45 -0.8 -1.2 v v ds =v gs , i d =-250 a g fs *1 - 9 - s v ds =-5v, i d =-5a i gss - - d 100 na v gs = d 12, v ds =0 - - -1 a v ds =-16v, v gs =0 i dss - - -25 a v ds =-16v, v gs =0, tj=125 c i d(on) *1 -10 - - a v ds =-5v, v gs =-4.5v - 51 58 m v gs =-4.5v, i d =-6a r ds(on) *1 - 75 90 m v gs =-2.5v, i d =-3a dynamic qg *1, 2 - 7 - qgs *1, 2 - 1.3 - qgd *1, 2 - 2.5 - nc i d =-6a, v ds =-10v, v gs =-4.5v t d(on) *1, 2 - 18 - tr *1, 2 - 35 - t d(off) *1, 2 - 40 - t f *1, 2 - 35 - ns v ds =-10v, i d =-1a, v gs =-4.5v, r g =6 ciss - 653 - coss - 102 - crss - 87 - pf v gs =0v, v ds =-10v, f=1mhz rg - 7.5 - v gs =15mv, v ds =0, f=1mhz source-drain diode i s *1 - - -10 i sm *3 - - -40 a v sd *1 - - -1.3 v i f =i s , v gs =0v note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping marking MTF50P02J3 to-252 (rohs compliant and halogen-freepackage) 2500 pcs / tape & reel f50p02
cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 3/7 MTF50P02J3 cystek product specification characteristic curves
cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 4/7 MTF50P02J3 cystek product specification characteristic curves(cont.)
cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 5/7 MTF50P02J3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 6/7 MTF50P02J3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c784j3 issued date : 2011.04.06 revised date : page no. : 7/7 MTF50P02J3 cystek product specification to-252 dimension inches millimeters inches marking: style: pin 1.gate 2.drain 3.source 3-lead to-252 plastic surface mount package date code device name cystek package code: j3 millimeters dim min. max. min. max. dim min. max. min. max. a 0.0827 0.0984 2.10 2.50 e 0.2520 0.2638 6.40 6.70 a1 0.0374 0.0512 0.95 1.30 e2 0.1890 0.2146 4.80 5.45 b 0.0118 0.0335 0.30 0.85 h 0.3622 0.3996 9.20 10.15 b1 0.0157 0.0370 0.40 0.94 l 0.0350 0.0669 0.89 1.70 b2 0.0236 0.0394 0.60 1.00 l1 0.0354 0.0650 0.90 1.65 c 0.0157 0.0236 0.40 0.60 l2 0.0197 0.0433 0.50 1.10 d 0.2087 0.2441 5.30 6.20 l3 0.0000 0.0118 0.00 0.30 d2 0.2638 0.2874 6.70 7.30 p 0.0827 0.0984 2.10 2.50 d3 0.0866 0.1181 2.20 3.00 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead : pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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